FPGA Implementation of 32 Tap FIR Filter with Multi Hierarchy Pipeline Architecture
نویسندگان
چکیده
This paper presents an efficient architecture for FIR filter using multi hierarchy pipelining. By choosing inner clock frequency several times more than the input sampling frequency multiply and accumulate components can be shared and hence the area and delay are optimized. An N tap FIR filter can be divided into N/M groups and two hierarchies of pipelining stages are inserted between N/M groups, within N/M groups and another five within a pipelined multiply and accumulate component (MAC). The design is implemented on vertex v50efg256-7 FPGA and the results presented, show that the proposed filter is optimized in area and delay.
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